Hardware description language

In electronics, a HDL (an acronym for hardware description language) is any language from a class of computer languages for formal description of electronic circuits. It can describe circuit's operation, its design, and tests to verify its operation by means of simulation.

A HDL is a standard text-based expression of the temporal behaviour and/or (spatial) circuit structure of an electronic system. In contrast to a software programming language, an HDL's syntax and semantics include explicit notations for expressing time and concurrency which are the primary attributes of hardware. Languages whose only characteristic is to express circuit connectivity between a hierarchy of blocks are properly classified as netlist languages.

Frequently (and incorrectly), the term programming is used to be synonymous with writing a hardware description. This often arises because of the goal that HDLs be executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements and the progression of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically. This execution capability makes it seem like the language is used to program something. Simulators capabable of supporting discrete event (digital), and continuous time (analog) modeling exist and HDL's targeted for each are available.

It is certainly possible to represent hardware semantics using traditional programming languages such as C?++ (and augmented with extensive and unwieldy class libraries.) However, the C++ language does not include any capability for expressing time explicitly and consequently is not a proper hardware description language.

Using the proper subset of virtually any (hardware description or software programming) language a software program called a synthesizer can infer hardware logic operations from the language statements and produce an equivalent netlist of generic hardware primitives to implement the specified behaviour. This typically (as of 2004) requires the synthesizer to ignore the expression of any timing constructs in the text. The ability to have a synthesizable subset of the language does not itself make a hardware description language.

HDLs have two purposes:

First, they are used to write a model for the expected behaviour of a circuit before that circuit is designed and built. The model is fed into a computer program, called a simulator, that allows the designer to verify that his solution behaves correctly.
Second, they are used to write a detailed description of a circuit that is fed into another computer program called a logic compiler. The output of the compiler is used to configure a programmable logic device that has the desired function. Often, the HDL code that has been simulated in the first step is re-used and compiled in the second step.

An HDL is analogous to a software programming language, but with subtle differences. Both types of language are processed by a compiler. An HDL compiler often works in several stages, first producing a logic description file in a proprietary format, then converting that to a logic description file in the industry-standard EDIF format, then converting that to a JEDEC-format file. The JEDEC file contains instructions to a PLD programmer for building logic.

On the other hand, a software compiler generates instructions to a microprocessor for moving data. The difference between HDLs and software languages is becoming less distinct as reconfigurable system?s are beginning (in 2002) to combine features of both.

HDLs used for digital circuit design include:

Verilog HDL
VHDL
ABEL HDL ("Advanced Boolean Expression Language", a proprietary language developed by the Data I/O Corporation and now owned by Lattice Semiconductor)
AHDL (Altera HDL, a proprietary language from Altera)
CUPL (a proprietary language from Logical Devices, Inc.)

There are attempts to create HDL for analog circuit design.

The current trend is to move away from proprietary HDLs and towards the two leading standards, VHDL and Verilog HDL.

There also exist attempts to create high-level description languages, i.e. high-level languages for low-level descriptions. Examples of this new work are:

Confluence (GNU GPL)
_Lava (Xilinx use Haskell for HDL)

From Wikipedia, the free encyclopedia

This page is linked from: FPGA OpenHW programmable logic device VHDL